In a circuitry, the values, especially the peak values and amplitudes, of some signals are usually needed for system control or other purposes. FIG. 1 schematically shows a prior art peak value sample and hold circuit 100. The peak value sample and hold circuit 100 samples the value of an input signal VIN, and generates an output signal VOUT indicating the peak value of the input signal VIN. The peak value sample and hold circuit 100 comprises: a power supply Vcc and a ground signal VGND; a PMOS (P-type Metal Oxide Semiconductor Field Effect Transistor) P1 with a source terminal coupled to the power supply Vcc and a drain terminal coupled to the output signal VOUT; a capacitor C1 coupled between the output signal VOUT and the ground signal VGND; a comparator 101 with a non-inverting input terminal coupled to the input signal VIN and an inverting terminal coupled to the output signal VOUT.
The operation of the peak value sample and hold circuit 100 in FIG. 1 is: (1) when the input signal VIN is larger than the output signal VOUT, the comparator 101 generates a logical low signal to turn ON the PMOS P1. As a result, the capacitor Cl is charged by the power supply Vcc, and the output signal VOUT increases until it reaches the input signal VIN. Thus the output signal VOUT increases as the input signal VIN increases. (2) when the input signal VIN decreases or remains unchanged, the output signal VOUT maintains because the capacitor couldn't be discharged. So the output signal VOUT stores the peak value of the input signal VIN. But in real application, the leakage current of the PMOS P1 may cause variation of the output signal VOUT. For example, a parasitic diode D1 coupled between the source and the drain of the PMOS P1 may charge the capacitor C1 because of its non-ideal cutoff characteristic, which results in an error of the output signal VOUT. For example, if the capacitance of the capacitor C1 is 100 pF, the leakage current of the PMOS P1 is 1 nA. After 20 ms, the increase of the output signal VOUT may be 0.2V. It is an unacceptable error in the most of the applications.
The present disclosure pertains to provide a precise and reliable sample and hold circuit.